The present invention relates generally to digital computers and, more specifically, to bus arbitration in digital computers.
As the performance demands on digital computers continue to increase at a meteoric pace, processors have been developed which operate at higher and higher clock speeds. The instruction sets used to control these processors have been pared down (e.g., RISC architecture) to make them more efficient. Processor improvements alone, however, are insufficient to provide the greater bandwidth required by computer users. The other computer subsystems which support the processor, e.g., I/O devices and memory devices, must also be designed to operate at higher speeds and support greater bandwidth. In addition to improved performance, cost has always been an issue with computer users. Thus, system designers are faced with the dual challenges of improving performance while remaining competitive on a cost basis.
Buses convey data and instructions between the elements of a digital computer. Commonly, three types or portions of buses are provided, i.e., control, address and data, each of which convey the different types of information connoted by their names. Local buses provide data transmission capability within a device, whereas system buses interconnect devices, such as I/O subsystems, memory subsystems and a central processor, together. In many systems, several devices compete for use of the system bus. In industry parlance, devices which can control the system bus are termed bus masters, while other devices, which are passive and respond to requests from the bus masters, are termed slaves. Some devices may operate at different times either as a slave or a bus master to accomplish different objectives.
In order to avoid bus contention, the situation where two bus masters have simultaneous control over the system bus, a bus arbiter can be provided to prioritize requests to use the bus. In such systems, a device which wishes to become a bus master will send a bus request signal to the arbiter over a dedicated line in the control bus. If the arbiter grants the bus request, then an acknowledgement or granting signal is transmitted back to the requesting device over another control line. The methodology by which the arbiter prioritizes requests is called the bus protocol. These protocols can be implemented as an ordered list of bus masters (i.e., the highest requesting bus master on the list receives a bus grant) or as state machines inside the arbiter.
In many conventional systems, the time periods during which a bus master controls the address bus (address tenure) and the data bus (data tenure) are the same. This concept is illustrated in FIG. 1 wherein the address tenures for memory cycles 1 and 2 are the same as the data tenures for those cycles. Cycles 3 and 4 are "address-only" cycles which are used by the system for operations which require address information but no other data. Since the address and data tenures are synchronized in these conventional systems, a joint arbiter suffices for these systems since only one transaction occurs at a time.
If the address was not continuously driven until the end of the data tenure, it would then be possible to begin another cycle, for example an "address-only" cycle which uses the address bus but not the data bus, while a previously initiated data cycle was being completed on the data bus. This type of overlapping address and data tenure (not shown in FIG. 1) is referred to as pipelining and can improve bus throughput. However, arbitration becomes correspondingly more complex when using pipelining, since arbitration of the data bus and the address bus can now differ. Moreover, if a split bus technology is used, different bus masters can use the address and data buses at the same time which further complicates arbitration issues.